High speed serial data designers are required to design robust and reliable receivers to meet the required Bit Error Rate (BER) for specified conditions. Receiver testing of any high speed serial data standard will include compliance testing and jitter tolerance testing. The compliance test comprises the testing of the receiver's performance for specified conditions to achieve the desired result. The tolerance tests involve subjecting the receiver to progressively increasing jitter until breakdown. The jitter can be classified as deterministic jitter Dj and random jitter Rj The deterministic jitter Dj is comprised of periodic jitter Pj, duty cycle distortion (DCD) and Intersymbol interference (ISI). ISI is inevitable in most physical systems due to limited bandwidth. Both DCD and ISI depend on the type of data stream and data rate. These are correlated with data and are classified as data dependent jitter (DDJ). Therefore to carry out compliance and jitter tolerance tests, it is important that the serial data is subjected to jitter in a controlled manner.
Intersymbol interference is currently generated using a circuit board on which signal traces are formed having various lengths, such as a differential Intersymbol interference (ISI) Test Board, manufactured and sold by Synthesys Research Inc., Menlo Park, Calif. One of the challenges of using such circuit boards is that the characteristic of the trace varies with the pattern and data rate. Further, the traces come with a Fixed ISI for a given data rate, hence it is not possible to generate intermediate ISI values. Typical trace lengths of a Synthesis Research ISI Test Board are 2.42″, 5″, 6.75″, 9″, 12″, 17″, 24″, 31″, and 40″ which does not allow for intermediate trace lengths between the set lengths. Normally, users would like to know the exact break point of their design but do not have the fine control over the ISI generated out of the ISI Test Board.
Another issue is that changing from one trace to another needs calibration. This is often time consuming because not only the ISI needs to be calibrated but all the other associated jitters, such as Pj and Rj, need to be calibrated. Additionally, the actual ISI output from the test board may not exactly match the ISI in the test board data sheet because of other components, such as connectors, cables and the like, in the test system which would interfere with the ISI generated. This requires the calibration of test system for each new test set-up.